Decreasing size and increasing functionality of consumer electronic devices, such as wireless communication devices, fuel an increasing demand for reliable integrated circuits (“IC”) with larger scale of integration, higher device density, lower power consumption and faster speed. However, ICs having increased scale of integration, density, and speed and decreased power consumption also require highly conductive and reliable interconnect lines. Consequently, copper has become more desirable as a replacement for aluminum in interconnect lines, since copper has a lower resistance, i.e. it is more conductive, compared with aluminum. The lower resistance of copper enables signals in the IC to move faster by decreasing the RC time delay in the IC's interconnect lines. Furthermore, since copper has a higher electromigration resistance compare to aluminum, copper interconnect lines can reliably handle higher current densities with thinner lines.
Copper interconnect lines can be fabricated by using copper damascene interconnect technology. In current copper damascene interconnect technology, a trench can be etched in an interlayer dielectric (“ILD”) film stack, and the sidewalls and bottom surface of the trench can be covered with a barrier metal, such as tantalum, which prevents copper from diffusing into the ILD film stack. Copper is then filled into the trench by electrochemical plating, and then a chemical mechanical polish (“CMP”) process can be used to remove excess copper and the barrier metal and provide a substantially planar surface over the copper-filled trench, which forms an interconnect line.
However, due to ILD film stack thickness variations and non-uniformity in the CMP process, the copper thickness can vary significantly from wafer to wafer and can also vary across the wafer after the CMP process. As a result, copper interconnect resistance, which is critical in many types of circuits, such as analog, digital, and speed sensitive circuits, can undesirably vary across the wafer and from wafer to wafer.
Thus, there is a need in the art for a method for reducing undesirable variations in copper interconnect thickness across a wafer and between wafers.